The present invention relates to a method of design for testability for integrated circuits (LSIs).
A typical example of the conventional method of design for testability includes a scan path method. In the scan path method, a flip-flop (FF) included in a logically designed LSI is replaced with a scan FF which can be externally directly controlled (scanned in) and observed (scanned out), so that a problem of a sequential circuit can be simplified into a problem of a combinational circuit. Thus, a test sequence can be easily generated ("Digital Systems Testing and Testable DESIGN, Chapter 9, Design For Testability", 1990, published by Computer Science Press).
However, such a conventional method of design for testability has the following problems:
(1) Since an FF is replaced with a scan FF, the LSI is increased in area. PA1 (2) Since a test input pattern for the scan-in/out operation on a scan chain is required, the number of test input patterns is increased, resulting in increasing time required for the test of the LSI. PA1 (3) Since an FF is replaced with a scan FF after logical design, it is necessary to examine the operation timing of the LSI again. According to circumstances, the LSI is required to be logically designed again, namely, so-called the re-design of the LSI is required. This elongates time for designing the LSI.